The present invention generally relates to floating gate memory devices such as an array of flash memory cells, and relates more particularly to a circuit architecture and method for programming NOR flash arrays to reduce column leakage associated therewith.
As is generally known, in recent years a new category of electrically erasable EPROMs/EEPROMs has emerged as an important non-volatile memory which combines the advantages of EPROM density with EEPROM electrical erasability and are sometimes referred to as xe2x80x9cflashxe2x80x9d EPROM or EEPROM. Flash memory devices typically include multiple individual components formed on or within a substrate. Such devices often comprise a high density section and a low density section. For example, as illustrated in prior art FIG. 1a, a memory device such as a flash memory 10 comprises one or more high density core regions 11 and a low density peripheral portion 12 on a single substrate 13. The high density core regions 11 typically consist of at least one Mxc3x97N array of individually addressable, substantially identical floating-gate type memory cells and the low density peripheral portion 12 typically includes input/output (I/O) circuitry and circuitry for selectively addressing the individual cells (such as decoders for connecting the source, gate and drain of selected cells to predetermined voltages or impedances to effect designated operations of the cell such as programming, reading or erasing).
The memory cells within the core portion 11 are coupled together in a NOR-type circuit configuration, such as, for example, the configuration illustrated in prior art FIG. 1b. Each memory cell 14 has a drain 14a, a source 14b and a stacked gate 14c. 
The NOR configuration illustrated in FIG. 1b has each drain terminal 14a of the transistors within a single column connected to the same bit line (BL). In addition, each flash cell 14 has its stacked gate terminal 14c coupled to a different word line (WL) while all the flash cells in the array have their source terminals 14b coupled to a common source terminal (CS). In operation, individual flash cells may be individually addressed via the respective bit line and word line using peripheral decoder and control circuitry for programming (writing), reading or erasing functions.
Prior art FIG. 1c represents a fragmentary cross section diagram of a typical memory cell 14 in the core region 11 of prior art FIGS. 1a and 1b. Such a cell 14 typically includes the source 14b, the drain 14a, and a channel 15 in a substrate or P-well 16; and the stacked gate structure 14c overlying the channel 15. The stacked gate 14c further includes a thin gate dielectric layer 17a (commonly referred to as the tunnel oxide) formed on the surface of the P-well 16. The stacked gate 14c also includes a polysilicon floating gate 17b which overlies the tunnel oxide 17a and an interpoly dielectric layer 17c overlies the floating gate 17b. The interpoly dielectric layer 17c is often a multilayer insulator such as an oxide-nitride-oxide (ONO) layer having two oxide layers sandwiching a nitride layer. Lastly, a polysilicon control gate 17d overlies the interpoly dielectric layer 17c. The control gates 17d of the respective cells 14 that are formed in a lateral row share a common word line (WL) associated with the row of cells (see, e.g., prior art FIG. 1b). In addition, as highlighted above, the drain regions 14a of the respective cells in a vertical column are connected together by a conductive bit line (BL). The channel 15 of the cell 14 conducts current between the source 14b and the drain 14a in accordance with an electric field developed in the channel 15 by the stacked gate structure 14c. 
According to conventional operation, the flash memory cell 14 operates in the following manner. The cell 14 is programmed by applying a relatively high voltage VG (e.g., approximately 9 volts) to the control gate 17d and connecting the source to ground and the drain 14a to a predetermined potential above the source 14b (e.g., approximately 5 volts). These voltages generate a vertical and lateral electric field along the length of the channel from the source to the drain. This electric field causes electrons to be drawn off the source and begin accelerating toward the drain. As they move along the length of the channel, they gain energy. If they gain enough energy, they are able to jump over the potential barrier of the oxide into the floating gate 17b and become trapped in the floating gate 17b since the floating gate 17b is surrounded by insulators (the interpoly dielectric 17c and the tunnel oxide 17a). As a result of the trapped electrons, the threshold voltage of the cell 14 increases, for example, by about 2 to 5 volts. This change in the threshold voltage (and thereby the channel conductance) of the cell 14 created by the trapped electrons is what causes the cell to be programmed.
To read the memory cell 14, a predetermined voltage VG that is greater than the threshold voltage of an unprogrammed or erased cell, but less than the threshold voltage of a programmed cell, is applied to the control gate 17d with a voltage applied between the source 14b and the drain 14a (e.g., tying the source 14b to ground and applying about 1-2 volts to the drain 14a). If the cell 14 conducts (e.g., about 50-100 xcexcA), then the cell 14 has not been programmed (the cell 14 is therefore at a first logic state, e.g., a zero xe2x80x9c0xe2x80x9d). Likewise, if the cell 14 does not conduct (e.g., considerably less current than 50-100 xcexcA), then the cell 14 has been programmed (the cell 14 is therefore at a second logic state, e.g., a one xe2x80x9c1xe2x80x9d). Consequently, one can read each cell 14 to determine whether it has been programmed (and therefore identify its logic state).
A flash memory cell 14 can be erased in a number of ways. In one arrangement, a relatively high voltage Vs (e.g., approximately 12-20 volts) is applied to the source 14b and the control gate 17d is held at a ground potential (VG=0), while the drain 14a is allowed to float. Under these conditions, a strong electric field is developed across the tunnel oxide 17a between the floating gate 17b and the source 14b. The electrons that are trapped in the floating gate undergo Fowler-Nordheim tunneling through the tunnel oxide 17a to the source 14b. In another arrangement, applying a negative voltage on the order of minus 10 volts to the control gate, applying 5 volts to the source and allowing the drain to float can also erase a cell. In a further arrangement, applying 5 volts to the P-well and minus 10 volts to the control gate while allowing the source and drain to float erases a cell.
As flash memory cells continue to be scaled down in size, the short channel effects of the memory cells may cause some cells to exhibit scaling induced leakage. For example, as illustrated in FIG. 2, when a program function is to be performed for a cell in the NOR array 11, for example, the flash memory cell 14, other cells 22, 24 and 26 associated with the same bit line BL1 have a bit line voltage of about 5V applied to their drain terminal. Thus the electric field across the channel of cells 22, 24 and 26 can, in some instances, generate hot carriers which contribute to leakage current (ILxe2x89xa00) on the bit line, and is sometimes referred to as column leakage.
Such leakage during programming is undesirable because it negatively impacts the program efficiency of the memory device. That is, due to the leakage of unselected cells along a given bit line, the drain charge pump which supplies the current for the programming of the cell 14 also provides the extra current associated with the leakage of the other cells (e.g., cell 22 as illustrated in prior art FIG. 3). Thus the flash memory consumes extra power during programming which is not utilized. Since flash memory devices are often used in portable applications such as cell phones and personal digital assistants (PDAs) which use batteries as power sources, such reductions in program efficiency are particularly undesirable. The issue of column leakage is significant because in many arrays or device sectors 512 flash cells are associated with each bit line (BL). Thus if each or many of the 511 non-selected cells in the bit line are exhibiting scaling induced leakage during programming, power dissipation may become significant.
There is a strong need in the art for a flash memory device structure, architecture and process for manufacture that improves the performance and reliability of the device.
The following presents a simplified summary of the invention in order to provide a basic understanding of some aspects of the invention. This summary is not an extensive overview of the invention. It is intended neither to identify key or critical elements of the invention nor to delineate the scope of the invention. Its primary purpose is to present some concepts of the invention in a simplified form as a prelude to the more detailed description that is presented later. The present invention relates to a circuit architecture and method of programming data in a flash memory in which column leakage associated therewith is greatly reduced or eliminated altogether.
According to one aspect of the present invention, a flash memory device having improved programming efficiency is disclosed. The device comprises a plurality of flash memory cells configured to form a NOR-type array architecture, wherein each of the plurality of memory cells have a source terminal which are coupled together to form a common source. The device further comprises a common source selection component (e.g., a transistor) which is coupled between the common source and a predetermined potential (e.g., Vss or circuit ground potential). The common source selection component is operable to electrically isolate the common source from the predetermined potential during a program mode of operation, thereby causing the common source to float. Isolating the common source during programming prevents flash memory cells associated with a bit line having the selected memory cell from experiencing short channel induced leakage, thereby improving the programming efficiency.
When the common source is floated during programming, the shared common source capacitance of the NOR-array causes the source of the selected cell to behave, for example, as a virtual ground for a period of time. During such time period, application of a programming voltage to the word line associated with the selected cell causes the selected cell to be programmed. With regard to the other cells coupled to the same bit line as the selected cell, hot carrier induced leakage is prevented or substantially reduced due to the increased impedance associated with the floating common source. Therefore the drain pump employed to provide current along the bit line of the selected cell provides programming current for the selected cell to be programmed, but not for leaky, non-selected cells associated with the activated bit line. Consequently, the amount of current supplied by the drain pump (and thus power consumption) during programming is reduced, thereby improving the programming efficiency.
According to another aspect of the invention, the memory device comprises a common source control circuit which is adapted to ascertain an operational mode of the device and configure the common source selection component in response thereto in order to float the common source of the NOR array during a program mode of operation. For example, the common source control circuit receives one or more input signals which are indicative of an operational mode of the device such as the program mode, read mode and erase mode. The common source control circuit then outputs a control signal to the common source selection component to electrically isolate the common source of the NOR array from a predetermined potential during the program mode.
According to yet another aspect of the invention, a method of programming a flash memory cell in a NOR type memory array comprises identifying a program mode of operation and floating the common source of the NOR array containing the selected cell during a program mode of operation. After floating the common source, the selected cell is programmed, thereby reducing hot carrier induced leakage current associated with non-selected cells on the same bit line as the programmed cell.
According to still another aspect of the present invention, the method of programming comprises determining an operational mode of the flash memory device and identifying a flash memory cell within the array as a selected cell for programming if the operational mode is determined to be the program mode. The method further comprises activating a bit line associated with the selected cell and activating a word line associated with the selected cell with a programming voltage after the common source is floated, thereby programming the cell. By ensuring that the common source is floated prior to coupling the programming voltage to the appropriate word line, hot carrier induced leakage associated with non-selected cells on the activated bit line is reduced or eliminated altogether.